嵌入式培训

嵌入式Linux就业班马上开课了 详情点击这儿

 
上海报名热线:021-51875830
深圳报名热线:4008699035
武汉报名热线:027-50767718
广州报名热线:4008699035
西安报名热线:029-86699670
南京报名热线:4008699035
成都报名热线:4008699035
北京报名热线:010-51292078
曙海集团研发与生产请参见网址:
www.shanghai66.cn
全英文授课课程(Training in English)
  首 页  手机阅读模式  课程介绍   培训报名  企业培训   付款方式   讲师介绍   学员评价  关于我们   联系我们   承接项目 开发板商城 
嵌入式协处理器--FPGA
FPGA项目实战系列课程----
嵌入式OS--4G手机操作系统
嵌入式协处理器--DSP
手机/网络/动漫游戏开发
嵌入式OS-Linux
嵌入式CPU--ARM
嵌入式OS--WinCE
单片机培训
嵌入式硬件设计
Altium Designer Layout高速硬件设计
嵌入式OS--VxWorks
PowerPC嵌入式系统/编译器优化
PLC编程/变频器/数控/人机界面 
开发语言/数据库/软硬件测试
3G手机软件测试、硬件测试
芯片设计/大规模集成电路VLSI
云计算、物联网
开源操作系统Tigy OS开发
小型机系统管理
其他类
WEB在线客服
南京WEB在线客服
武汉WEB在线客服
西安WEB在线客服
广州WEB在线客服
点击这里给我发消息  
QQ客服一
点击这里给我发消息  
QQ客服二
点击这里给我发消息
QQ客服三
  双休日、节假日及晚上可致电值班电话:021-51875830 值班手机:15921673576/13918613812

值班QQ:
点击这里给我发消息

值班网页在线客服,点击交谈:
 
网页在线客服

 
公益培训通知与资料下载
企业招聘与人才推荐(免费)

合作企业新人才需求公告

◆招人、应聘、人才合作,
请把需求发到officeoffice@126.com或
访问曙海旗下网站---
电子人才网
www.morning-sea.com.cn
合作伙伴与授权机构
现代化的多媒体教室
曙海集团招聘启示
曙海动态
邮件列表
 
 
     Design Compiler高级培训班(Synopsys)
   班级规模及环境--热线:4008699035 手机:15921673576/13918613812( 微信同号)
       为了保证培训效果,增加互动环节,我们坚持小班授课,每期报名人数限5人,多余人员安排到下一期进行。
   上课时间和地点
上课地点:【上海】:同济大学(沪西)/新城金郡商务楼(11号线白银路站) 【深圳分部】:电影大厦(地铁一号线大剧院站)/深圳大学成教院 【北京分部】:北京中山/福鑫大楼 【南京分部】:金港大厦(和燕路) 【武汉分部】:佳源大厦(高新二路) 【成都分部】:领馆区1号(中和大道)
近开课时间(周末班/连续班/晚班)
Design Compiler高级培训班:即将开课,详情请咨询客服。..(欢迎您垂询,视教育质量为生命!)
   实验设备
     ◆课时: 一个月

        
        ☆合格学员免费颁发相关资格证书,提升您的职业资质
        作为早专注于嵌入式培训的专业机构,曙海嵌入式提供的证书得到本行业的广泛认
        可,学员的能力得到大家的认同

        ☆合格学员免费推荐工作
        ★实验设备请点击这儿查看★
   新优惠
       ◆在读学生凭学生证,可优惠500元。
   质量保障

        1、培训过程中,如有部分内容理解不透或消化不好,可免费在以后培训班中重听;
        2、课程完成后,授课老师留给学员手机和Email,保障培训效果,免费提供半年的技术支持。
        3、培训合格学员可享受免费推荐就业机会。

  Design Compiler高级培训班(Synopsys)
  课程描述

       DC是把HDL描述的电路综合为跟工艺相关的、门级电路。并且根据用户的设计要求,在时序和面积,时序和功耗上取得佳的效果。在floor planning和placement和插入时钟树后 返回DC进行时序验证。其高版本被称为DC Ultra。在Synopsys软件中完整的综合方案的核心是DC UltraTM,对所有设计而言它也是好级别的综合平台。DC Ultra添加了全面的 数据通路和时序优化技术,并通过工业界的反复证明。

   课程内容

 第一阶段

       综合的定义;ASIC design flow;Synopsys Design Compiler的介绍;Tcl/Tk 功能介绍;Synopsys technology library;Logic synthesis的过程;Synthesis 和layout的接口——LTL;Post_layout optimization;SDF文件的生成;其他高级综合技巧与总结。

  Overview?
  
   This course covers the ASIC synthesis flow using Design Compiler -- from reading in an RTL design (Verilog and VHDL) to generating a final gate-level netlist. You will learn how to read in your design file(s), specify your libraries, constrain a complex design for area and timing, partition your design? hierarchy for synthesis, apply synthesis techniques to achieve area and timing closure, analyze the synthesis results, and generate output data that works with downstream layout tools. You will verify the logic equivalence of synthesis transformations (such as Datapath optimizations and Register Retiming) to that of an RTL design using Formality. The course includes labs to reinforce and practice key topics discussed in lecture. All the covered commands and flows are printed separately in a 4-page Job Aid which the student can refer to back at work.
  
   Objectives?
  
   At the end of this workshop the student should be able to:?
   ◆Create a setup file to specify the libraries that will be used?
   ◆Read in a hierarchical design?
   ◆Partition a design's hierarchy optimally for synthesis?
   ◆Constrain a complex design for area and timing, taking into account different environmental attributes such as output loading, input drive strength, process, voltage and temperature variations, as well as post-layout effects such as clock skew and net parasitics?
   ◆Select the appropriate compile flow for your project?
   ◆Execute the recommended synthesis techniques within each compile flow to achieve area and timing closure?
   ◆Perform test-ready synthesis when appropriate?
   ◆Verify the logic equivalence of a synthesized netlist to that of an RTL design?
   ◆Write DC-Tcl scripts to constrain and compile designs?
   ◆Generate and interpret timing, constraints and other debugging reports?
   ◆Understand the effect that RTL coding style can have on synthesis results?
   ◆Generate output data (netlist, timing/area constraints, physical constraints scan-def) that works with downstream physical design?or?layout tools?
  
   Audience Profile
  
   ASIC digital designers who are going to use Design Compiler to synthesize Verilog?or?VHDL RTL modules to generate gate-level netlists.
  
   Prerequisites
  
   To benefit the most from the material presented in this workshop, you should:
   ◆Understand the functionality of digital sequential and combinational logic?
   ◆Have familiarity with UNIX and a UNIX text editor of your choice?
   ◆No prior Design Compiler knowledge?or?experience is needed?
  
  第二阶段
  
   Unit 1
   ◆Introduction to Synthesis
   ◆Setting Up and Saving Designs
   ◆Design and Library Objects
   ◆Area and Timing Constraints
   ◆Setting Up and Saving Designs

  • Loading Technology and Design Data
  • Design and Library Objects
  • Timing Constraints



   Unit 2
   ◆Partitioning for Synthesis
   ◆Environmental Attributes
   ◆Compile Commands
   ◆Timing Analysis
   ◆More Constraint Considerations
  

  • Compiling RTL to Gates
  • Timing Analysis


Unit 3
◆More Constraint Considerations
◆Multi-Clock Designs
◆Synthesis techniques and Flows
◆Post-Synthesis Output Data
◆Conclusion
Congestion Analysis and Optimization

Unit 4

Unit 5

Clock Tree Synthesis

Multi Scenario Optimization

?

Unit 6

Design Planning

Routing and Crosstalk

Chip Finishing and DFM

Customer Suppor

第三阶段

第一部分
unit 1. Introduction to Synthesis
? Execute the basic steps of synthesis on a simple design
? Use two commands to modify the partitioning of a design
? Gain familiarity with SolvNet ,your essential resource for?
  solving your design compiler problems
unit 2. Setup, Libraries and Objects
unit 3. Partitioning for Synthesis
unit 4. DC Tcl - An Introduction

第二部分
unit 5. Timing and Area
?Constrain simple designs for area, timing and design
  rule constraints (DRC)
? Generate ,view and analyze timing and DRC reports
unit 6. Environmental Attributes
unit 7. Design Rules and Min Timing
unit 8.Timing Analysis

第三部分
unit 9.Multiple Clock/Cycle Designs
? Constrain and analyze multi-clock,
  asynchronous and multi-cycle path designs
? State several key steps that occur during a default compile?
? Enable Design Compiler to work harder in fixing design violations
? Describe some issues that surround synthesis and where to find additional information?

unit 10. Optimization

unit 11.Compile Strategies

unit 12. Before,During and After
 

   培养对象

        从事ASIC 设计与验证的工程师,希望更深入了解Design Compiler和芯片综合(chip synthesis)技术的工程师,希望从事ASIC设计工程师的理工科背景大四学生或硕士研究生。

   入学要求

        学员学习本课程应具备下列基础知识:
        ◆ 对数字集成电路设计有一定理解;
        ◆ 了解Verilog/VHDL 语言。

 
版权所有:曙海信息网络科技有限公司 copyright 2000-2010
 
上海总部培训基地

地址:上海市云屏路1399号26#新城金郡商务楼310。
(地铁11号线白银路站2号出口旁,云屏路和白银路交叉口)
邮编:201821
热线:021-51875830 32300767
传真:021-32300767
业务手机:15921673576/13918613812
E-mail:officeoffice@126.com
客服QQ: 849322415
北京培训基地

地址:北京市昌平区沙河南街11号312室
(地铁昌平线沙河站B出口) 邮编:102200 行走路线:请点击这查看
热线:010-51292078 57292751
传真:010-51292078
业务手机:15701686205
E-mail:qianru@51qianru.cn
客服QQ:1243285887
深圳培训基地

地址:深圳市环观中路28号82#201室

热线:4008699035
传真:4008699035
业务手机:13699831341

邮编:518001
信箱:qianru2@51qianru.cn
客服QQ:2472106501
南京培训基地

地址:江苏省南京市栖霞区和燕路251号金港大厦B座2201室
(地铁一号线迈皋桥站1号出口旁,近南京火车站)
热线:4008699035
传真:4008699035
邮编:210046
信箱:qianru3@51qianru.cn
客服QQ:1325341129
 
成都培训基地

地址:四川省成都市高新区中和大道一段99号领馆区1号1-3-2903 邮编:610031
热线:4008699035 业务手机:13540421960
客服QQ:1325341129 E-mail:qianru4@51qianru.cn
武汉培训基地

地址:湖北省武汉市东湖高新技术开发区高新二路128号(湖北第二师范正大门对面) 佳源大厦一期A4-1-701 邮编:430022
热线:4008699035
客服QQ:849322415
E-mail:qianru5@51qianru.cn
广州培训基地

地址:广州市越秀区环市东路486号广粮大厦1202室

热线:4008699035
传真:4008699035

邮编:510075
信箱:qianru6@51qianru.cn
西安培训基地

地址:西安市南二环东段31号云峰大厦1503室

热线:029-86699670
业务手机:18392016509
传真:029-86699670
邮编:710054
信箱:qianru7@51qianru.cn

双休日、节假日及晚上可致电值班电话:021-51875830 值班手机:15921673576/13918613812


备案号:沪ICP备08026168号

.(2014年4月12)............................................................................................................................................
在线客服